perm filename LRM.MSG[MUD,SYS] blob
sn#548962 filedate 1980-12-12 generic text, type C, neo UTF8
COMMENT ⊗ VALID 00020 PAGES
C REC PAGE DESCRIPTION
C00001 00001
C00004 00002 ∂23-Apr-79 0102 LLW Request for 64 K MOS RAM Technical Specs and Samples
C00007 00003 ∂03-May-79 0653 HWC
C00013 00004 I talked to Bob McInterff about the new 16k single 5v P.S. ram
C00033 00005 ∂14-Aug-79 1113 PN Introducing PAS, a pseudo-monitor (Away with all DO files!)
C00037 00006 ∂26-Sep-79 0104 JRS Current RAM Status
C00051 00007 βcancel-79 1049 JRS Wire Connection of ECL Inputs to Vcc
C00055 00008 ∂01-Oct-79 1750 HWC
C00056 00009 ∂06-Mar-80 0930 WRB
C00075 00010 ∂06-Mar-80 0930 WRB
C00079 00011 ∂06-Mar-80 1402 JBR Resolution pattern
C00082 00012 ∂26-Apr-80 1854 HWC Sail line wedging
C00089 00013 ∂09-Jun-80 1616 CBF New Instructions for rebooting the switch
C00091 00014 ∂16-Jun-80 1151 SJC Rebooting switch
C00110 00015 ∂19-Aug-80 0333 CBF Arpanet
C00120 00016 ∂03-Sep-80 0311 OTA ARPa net
C00128 00017 ∂05-Sep-80 1630 JBR SAIL disk pack
C00130 00018 ∂22-Sep-80 0134 JBR
C00138 00019 ∂08-Oct-80 1715 RFP 10k and 100k ecl inventory.
C00143 00020 ∂05-Nov-80 0223 LLW MEM2 Debut Rejoicing
C00162 ENDMK
C⊗;
∂23-Apr-79 0102 LLW Request for 64 K MOS RAM Technical Specs and Samples
To: LRM at SU-AI
CC: "@MARK2A[DIS,S1]" at SU-AI
Rich, to the extent that you haven't done so already, please promptly
order both complete technical specifications and sample quantities (3-5
each) for 64 K-bit nMOS RAMs from the following manufacturers, all of whom
have announced that they are offering/going to offer such a part:
1) Mostek (who is claiming <=100 nsec read access times with 1980
availability for their MK4164 part, with transparent refresh capability)
2) Motorola MCM6664
3) Texas Instruments TMS4164
4) Intel
5) National Semiconductor
6) Nippon Electric Co.
7) Hitachi
I am interested in quotes on delivery time and price as a function of when
we request delivery (e.g., Sept. 79, Dec. 79, etc.), time when production
lots will be available, etc. If they can't get you any of this, at least
get preliminary technical data sheets from all of them. We need these
data to plan for both the Mark IIA BSMs and for the secondary caches of
the Mark IIAs themselves.
Thanks,
Lowell
∂03-May-79 0653 HWC
To: LRM at SU-AI, OTA at SU-AI, DLW at SU-AI
∂08-Mar-79 0247 CEH at MIT-MC (Charles E. Haynes)
Date: 8 MAR 1979 0546-EST
From: CEH at MIT-MC (Charles E. Haynes)
To: C100-FANS at MIT-MC
I talked to HDS and finally found a way to shorten the feep.
There is a diode and two resistors immediately to the right of the feeper,
the farthest right resistor (160k ohms) controlss the length of the feep.
I put in a 100k trim pot in series with a 10k resistor in place of it.
I can now adjust the feep from about 1/10 second to almost a full second.
The volume and frequency are, unfortunately, fixed.
Charles
ps. this mod has no effect on the kbd clicker, it just shortens the bell.
I talked to Bob McInterff about the new 16k single 5v P.S. ram
chip, called "2118". The spec sheets are on there way, and prices are as
follows.
access time units of 100 units of 1000
100ns $46.05 $40.00
120ns $33.15 $28.20
150ns $27.65 $23.50
I asked Bob to send me along with the spec sheets a cost and
delivery time for 6k chips, if I were to orders them today.
LRM.
I Just received a call from Bob McInterff regarding the price
and delivery of 6k chips.
Delivery time if ordered now is 6 weeks for the first 1000
and two to three week between each successive 1000. Prices are as follows
100ns $31.40
120ns $22.60
150ns $18.85
Sarry about the confusion regarding the 6k notation. That is meent to
imply 6 thousand units of 16k bit rams.
A requist for 2 samples was made by TM, and passed onto
Bob McInterff. Bob will get back to me about the samples.
∂14-Aug-79 1113 PN Introducing PAS, a pseudo-monitor (Away with all DO files!)
To: S1 at SU-AI
I was typing [DO,S1] for the 2,436th time two days ago, and decided I
couldn't take it any more. The result is PAS, a combination of SNAIL and
DO that can be used to compile and run Pascal and Fortran programs at SAIL
using the S-1 Pascal system.
Some examples:
R PAS;FNAME (compiles FNAME.PAS or FNAME.FOR and runs it on the simulator)
EX (usually re-executes last PAS command (also control-X G from
the editor))
R PAS (ALWAYS re-executes the last PAS command)
R PAS;FNAME.PCO (put FNAME.PCO through SOPA and run it on the simulator)
R PAS;FNAME/C100000 (when running on simulator, increase core to 100000)
R PAS;FNAME/PS1/E (translate FNAME.PAS to FNAME.PS1 and edit the result)
R PAS;FNAME/OUT (compile and run FNAME.PAS, feeding FNAME.OUT to FSIM
for the Pascal output file)
R PAS;FNAME.LDI/TTYOUT (run FNAME.LDI on simulator, use "TTY:" for output)
R PAS;FNAME/U (use U-code system instead of P-code system)
R PAS;FNAME/O (run U-code through the optimizer)
R PAS;FNAME/INT/E (compile FNAME.PAS into U-code, run it on the interpreter,
using FNAME.OUT for OUTPUT, then look at the result)
R PAS;FNAME/LDI/D (don't say "END" to debugger when running SOPA (D stands
for "DEBUG")
R PAS;FNAME.LDI/FOR/RIM (load FNAME.LDI using Fortran run-times and write
out the RIM file)
R PAS;? (display HELP file)
For more details, type READ PAS.
∂26-Sep-79 0104 JRS Current RAM Status
To: "@MARK2A[DIS,S1]" at SU-AI
This file contains information on the RAMs that will possibly
be used in the MarkIIa.
Access Part
Size Time Number Comments
Fairchild
1024x1 20 10415A Normal delivery at this time.
15 to 18 weeks
4096x1 30(typ) 10470 In production but sold out for 1979.
Delivery for 200 pieces is 1st or 2nd
quarter 1980.
1024x1 15(∞ 100415 Die shrink on the 10415 with both a
10K and a 100K bias network on the
chip. Possible improvement in access
time to 15ns. Some working parts now.
256x4 10 100422 A few prototype parts done. 2 of
4 channels will not meet write enable
pulse width times. Will have to go
back for another iteration of mask.
Expect samples in Dec. and production
in 1st quarter of 1980.
Fujitsu
256x4 10 7071H In stock with distributors for both
12 7071N 'N' and 'H' versions. Delivery is
stock to 8 weeks for 2000 items.
1024x4 25 7077 This part is back on their list again.
They expect samples in 4th Q 79 and
production in 2nd Q 80.
Hitachi
1024x1 20 2110-2 In stock with distributors.
1024x1 7 2112 There is still no price or delivery
information available.
Motorola
256x4 12 10422 Parts to be sampled within the next
month. Production expected 4 Q 79.
4096x1 25 10470 Sample 1 Q 80. Production 2 Q 80.
1024x4 20 ----- Sample 2 Q 80. Production 3 Q 80.
National
256x4 12 100422 Sample Dec. 79. Production 3 Q 80.
National has cancelled plans to second
source 100K.
Joe
βcancel-79 1049 JRS Wire Connection of ECL Inputs to Vcc
To: "@MARK2A[DIS,S1]" at SU-AI
The following information was gathered due to a request
from TM and JBR. The question was ' Is it permissible design
practice to ground an input pin of ECL to provide a logical
high at that pin π.
Motorola- Although during the early ECL families it was commonally
done, wiring inputs to Vcc is not sound design practice.
The SSI parts of the 10K family will probilly tolerate
input grounding and still function correctly. The MSI parts in
the 10K family may not function properly. This is due to a bias
shift caused by the increased current drawn by the input
transistor. Two parts, the 10136 and 10137, are known to
malfunction if certain inputs are returned to Vcc.
The 10141 has also malfunctioned but not as solidly as the other two.
On these three parts, the inputs that are sensitive are the
'select' inputs.
The general feeling was that there would not be any short term
damage to the chips but that long term reliability could suffer.
Fairchild-
10K- They have reconised this problem and some chips have been
designed to permit inputs to be returned to Vcc.
See page 7-58 of their ECL Data Book. (The select lines of the 10136
and 10137). In general, inputs should not be tied to Vcc unless
spefically stated in the data sheet.
100K- From the design group at Fairchild. -NO-. Very
emphatically. Inputs to Vcc will cause some/most chips to cease
to function. Short term input ties to Vcc may not damage
the chips but long term ties may/will. The higher currents that
are used in 100K, along with smaller geometries, make the 100k
less tolerant to overvoltage and overcurrent.
Comment- The general feeling was that short term (several seconds
to several minutes) connection of the inputs to Vcc will not be
harmful but may cause malfunction (logically) of the chip. The 100K
people are much less comfortable in this position but admit that
it is done in testing. Long term effects are very suspect.
Joe
∂01-Oct-79 1750 HWC
To: "@PLAN[DIS,S1]" at SU-AI
∂08-Aug-79 0838 LRM
To: "@PLAN[DIS,S1]" at SU-AI
One of the following two phone numbers should be used incase trouble
should occur on the data line to SAIL.
For normall hours call 422-0027
For off hours call 276-3472
The data line lable is 1GD6523
[276-3472 should be 278-3472. -hwc]
∂06-Mar-80 0930 WRB
∂06-Mar-80 0852 WRB Memory Parts
To: JRS
CC: LLW, JBR, TM, PMF, WRB
I have started a file, MEM[1,wrb], which contains a summary of most of the
parts needed to construct a new memory system. This file contains the number
of parts needed and the number of parts of each kind that are currently
on hand in the palace. This list is currently incomplete although I am adding
to it as the information becomes available to me. Once the PC board PO is
out I will take responsibility for trying to speed delivery of the parts.
Bill
∂06-Mar-80 0930 WRB
∂06-Mar-80 0325 LLW Requisition for Another S-1 Memory
To: JRS
CC: LLW, PMF, JBR, TM, LCW, WRB
Dear Joe:
At Tuesday afternoon's MARK2A meeting, it was decided to commence the very
high priority construction of another 2 MW capacity S-1 Memory. There
were a number of reasons behind this decision, the primary one being the
(perceived) near-necessity for a total of 4 MWs of capacity being attached
to the Mark I to compile the Mark IIA design at all efficiently.
JBR and TM assumed the responsibility for designing the required BSM
controller to interface the two memory boxes to the Mark I, and will of
course need implementation support from your group. You are being asked
to supervise the RUSH replication of the present S-1 Memory, commencing
with the procurement of the needed RAMs, TTL, PC boards, etc.
In order to maximize the likelihood of the full 4 MW being really
available when we need it, and to minimize the loss of professional time
in getting it, we decided to essentially exactly replicate the present
system, with *no* (non-trivial) modifications or upgrades. Furthermore,
since there is adequate reserve in the present power supply, a basic spec
on the second memory box is that it will share the power supply of the
present one, and that a second power supply will be retrofitted at leisure
after the Mark IIA wirelist has gone out.
The urgency of this implementation is such that it should have the
full-time effort of both Rich and Ron (Roland remaining committed to
full-time effort on the ECL characterization work). 'Fancy', readily
isolatable features of the present memory box (e.g., the bus bars on the
side of the memory compartment itself) should be scrapped out of the
re-implementation, for the sake of minimizing implementation time.
Please get the requisitions for the long-lead-time items (PC boards, 6
megabytes of RAMs, etc.) prepared as soon as possible, for me to get
signed, and start the technicians to building the memory compartment and
installing it in a rack.
Thanks,
Lowell
∂06-Mar-80 1402 JBR Resolution pattern
Procedure for putting resolution pattern on GDP
1. From any switch terminal other than the GDP type
\O11<return>
2. If the response was IN USE job/tty/idle x y z then
if the GDP is up go to the GDP keyboard and type \Q<return>
and go back to #1.
If the GDP is not up type \M<return> Kx<return> Q
where x is the job number from the IN USE message.
Go back to 1.
3. The response is O OPEN. Type
\SB<return>
you should get a number and an @
4. Type RS/340<return>
R6/1000<return>
R7/173000<return>
P
you should get a $
5. Type AL<return>
6. Wait 5 seconds
7. Type \SD<return>
8. Close the connection \C<return> and open device 6 \O6<return>
9. Type a few calls (↑C) to make sure you are in RT11, then type
ASS RK1 DK<return>
R XPATCH<return>
DACTUN.LDA/G<return>
10. If you are doing this from the datamedia in the machine room
then you must make sure that parity is cleared. Type \P<return>
you will get either "parity transmitted" or "parity cleared".
If you got "parity transmitted" type \P<return> again and you
will get "parity cleared".
11. Type ↑Z↑V to start the transfer.
12. Close the connection \C<return> and open device 11 \O11<return>
13. Two asterisks will come out on the screen when the program finishes
loading if you did step 12 fast enough.
14. Follow the direction displayed on the GDP screen except that the
typing is not done on the GDP keyboard, it is done on the same
keyboard that has device 11 open.
k
∂26-Apr-80 1854 HWC Sail line wedging
To: "@PLAN[DIS,S1]" at SU-AI
Until the backplane of the Switch is rearranged, wedging of
the Sail line may be fixed by using the maintenance mode.
175610/ 30346 ;if this is x1xxxx instead of x3xxxx, hit little
;black reset button on left side of micom
; xxx3xx instead of xxx100 means an interrupt
; was lost.
175612/ xxxxxx ; this will typically be 14xxxx when wedged
175614/ 200 ;write 100 into this location to restart output
175616/ ;mostly irrelevent to this discussion
∂09-Jun-80 1616 CBF New Instructions for rebooting the switch
To: "@NET[DIS,S1]" at SU-AI
Rebooting the Switch
1) Place the Boot/Run switch in the Boot position. The DatMedia across
from the S-1 should now be talking to device 7.
2) Hit the reset button on the switch. A $ should come out on the TI.
Type AL170010 in response to the $. Wait 5 seconds.
3) Go to the DataMedia and type at device 7:
R XPATCH xpatch should prompt with a *, then type:
SY:SWITCH.BIN/U:177550 xpatch will type stuff about ↑Z↑X etc.
type ↑Z↑V (that is Control-Z Control-V)
4) The switch should come up in less than 30 seconds.
Type ↑Z↑X (Control-Z Control-X) followed by a ↑C (Control-C)
to exit XPATCH on device 7.
Reset the Boot/Run switch back to the run position.
SWITCH.DOC[1,CBF] -CBF 9 June 1980
∂16-Jun-80 1151 SJC Rebooting switch
To: "@PLAN[DIS,S1]" at SU-AI
After rebooting the switch, please remember to make the following patch:
Address Old value New value
5742 41420 41436
5756 41404 41422
Failure to patch these locations prevents rebooting the GDP.
∂19-Aug-80 0333 CBF Arpanet
To: "@NET[DIS,S1]" at SU-AI
Service has been restored. S1LPT should be back up. Report
any problems.
∂03-Sep-80 0311 OTA ARPa net
To: "@NET[DIS,S1]" at SU-AI
The recent problems that have been plaguing Device 6 FTP have been fixed.
Please let me know if you encounter any problems where FTPing a file
to Dev 6 introduces any errors into the file. Also the problem of
losing characters on typin may have gone away.
I have noticed recently that the ARPA machine sometimes BPTs at location
FNDSKT+322. Especially after calling out of FTP. Let me know if this
happens to you. If I'm not around just type start$g to get things going
again.
∂05-Sep-80 1630 JBR SAIL disk pack
To: WRB, JRS, LRM
I just spoke with Rob Poor at SAIL and he said that they really don't like
Nashua disk packs. They much prefer Dysan. He would like for us in the future
to avoid buying any more Nashua packs to be used at SAIL. If need be we can
specify that Stanford will not accept Nashua disk packs any more. The Inmac
pack we just received turns out ot be a Nashua pack.
--jeff
∂22-Sep-80 0134 JBR
could you please screw in the EIA connector going into the second slot
in the GDP room? Thanks, --jeff
∂08-Oct-80 1715 RFP 10k and 100k ecl inventory.
To: "@LOCAL[1,CEG]" at SU-AI
At the present these are the totals of the 10K and 100K inventory.
100K←←←←←← 10K←←←←← 10K←←←←←
type quan. type quan. type quan.
145 208
000 25 153 235
101 697 014 25 158 277
102 197 016 189 159 169
107 490 100 0 160 510
112 394 101 646 161 67
114 0 102 25 162 136
117 197 103 34 163 173
118 47 104 123 164 2495
122 0 105 453 165 231
123 47 106 25 166 14
130 47 107 549 170 209
131 47 109 497 171 120
136 97 110 702 172 25
141 796 111 544 173 1415
142 297 113 265 174 941
145 227 114 45 175 197
150 47 115 122 176 397
151 47 117 141 179 193
155 997 118 133 180 119
156 77 119 98 181 136
158 447 121 121 186 134
160 47 123 25 195 741
163 358 124 0 197 450
164 995 125 0 210 200
165 50 129 5 211 117
166 97 130 166 212 225
170 47 131 273 216 85
171 697 132 133 231 115
179 97 134 146 405 133
180 547 135 24 415 399
181 97 136 128 mb7042 47
182 597 141 2820 2147 419
183 297
∂05-Nov-80 0223 LLW MEM2 Debut Rejoicing
To: JBR, TM
CC: LLW, PMF, LCW, WRB, LRM, JRS
I am most pleased to announce that the Widdoes Memory Annex staggered to
its feet (would you believe "struggled to its knees") a few minutes ago,
with Bill and Rich crucially in attendance. The Mark I system now runs
MEMTST properly in MEM1, and MEM2 and the BSM await the ministrations
later today of their creators in order to bring themt into full
functionality.
Special thanks go to Rich for coming back this evening (after driving his
car pool home) and working through now in order to avoid the loss to the
Project of another day of Mark I system time.
Lowell
∂10-Nov-80 1320 TM Thanksgiving Dinner
To: "@PARTY[1,TM]"
CC: TM
You are all invited to my house on Thursday November 27 (5665 Bridgeport
Cr.) for Thanksgiving dinner at 7:00 pm. RSVP required by this Friday so
that the food can be ordered and prepared.
Tom
∂12-Nov-80 0721 Purger
You are exceeding your disk quota.
Files that occupy space beyond your quota are subject to purging.
If you don't delete some of your files, the purger will.
Your disk quota is: 5
Your files occupy 131
∂12-Nov-80 0728 Purger
To: S1 at SU-AI
You are exceeding your disk quota.
Files that occupy space beyond your quota are subject to purging.
If you don't delete some of your files, the purger will.
Your disk quota is: 9000
Your files occupy 11038
∂14-Nov-80 1554 SJC Controversial feature of MD
To: "@PLAN.[DIS,S1]"
We are inviting everyone who hasn't already done so to read
MDLED.DOC[DOC,TAW], a description of a line editor to be implemented
within the hardware debugger, and to comment on it.
∂14-Nov-80 1608 SJC Controversial extensions
To: "@PLAN.[DIS,S1]"
Correction to previous message: MDLED.TXT[DOC,TAW]. Apologies.--Steve
∂16-Nov-80 1922 HWC S1LPT on Dev6 and Dev7
To: "@PLAN.[DIS,S1]"
There is a version of S1LPT on Devs 6 and 7. It is similar to the SAIL one
and gives help on /?. The Dev6 one will only work when using Version 3.
Type "R S1LPT" to invoke it.
∂19-Nov-80 1018 TAW S-1 Mark II Machine Debugger
To: "@PLAN.[DIS,S1]"
A proposed command set for the Machine Debugger (MD) is available
in MD.DOC[FE,SJC]. Your comments and questions are solicited.
Further MD things of interest will be sent via the MD distribution
list located in MD.DIS[DIS,S1]. If you are interested, please place yourself
on that list. -- Tom
∂19-Nov-80 1034 PMF
To: "@PLAN.[DIS,S1]"
On Monday, Nov. 24, Allan Miller (Stanford), Lionel Pober and James Kerns
(Hughes) will visit. They have been working on a graphics terminal for
design aid software. They are (somewhat) interested in working here.
∂24-Nov-80 0833 CBF Device 7
To: "@NET.[DIS,S1]" at SU-AI
Device 7's disk is behaving poorly. This means that if any machines
in the local network (Switch, Grinnell, Arpa, LPT etc.) go down, it
could be very painful reloading them. Beware.
∂26-Nov-80 0106 Purger
You are exceeding your disk quota.
Files that occupy space beyond your quota are subject to purging.
If you don't delete some of your files, the purger will.
Your disk quota is: 5
Your files occupy 132
∂26-Nov-80 0118 Purger
To: S1 at SU-AI
You are exceeding your disk quota.
Files that occupy space beyond your quota are subject to purging.
If you don't delete some of your files, the purger will.
Your disk quota is: 9000
Your files occupy 10775
∂26-Nov-80 1436 SJC Swill shortage
To: "@PLAN.[DIS,S1]"
As far as I can determine, we have exactly six (6) copies of the FY78
green book (the four-inch thick edition) left in the transportainers. If
anyone knows of an additional cache of them, please either tell me or hide
them for the sake of posterity. Meanwhile, I propose to send out the
remaining copies only if someone needs material which is in the FY78 book
but *not* superseded by the FY79 book. General thrill-seekers will have
to wait for the latter.
We seem to have lots of FY78 microfiche left.--Steve
∂03-Dec-80 1817 Purger
You are exceeding your disk quota.
Files that occupy space beyond your quota are subject to purging.
If you don't delete some of your files, the purger will.
Your disk quota is: 5
Your files occupy 133
∂03-Dec-80 1829 Purger
To: S1 at SU-AI
You are exceeding your disk quota.
Files that occupy space beyond your quota are subject to purging.
If you don't delete some of your files, the purger will.
Your disk quota is: 9000
Your files occupy 11052
∂03-Dec-80 2037 PMF
To: "@PLAN.[DIS,S1]"
We are going to try to get the accounts and disk
store storage straightened out. If you feel the need for more (or less)
space and/or Sail thinks you are UNKNOWN, send me a message.
∂05-Dec-80 0312 LLW PMF As The Project's SAIL Coordinator
To: "@PLAN.[DIS,S1]"
In case it hasn't been clear hitherto, PMF will continue to serve as the
Project's SAIL Coordinator, the designated conduit for complaints,
requests for disc allocation, etc. If you don't get what you feel you
need in the way of SAIL services by sustained petitioning of Mike, you can
let TM or me know. *Do not* hassle the SAIL staff yourself!
Lowell
∂12-Dec-80 1315 RFP
To: "@LOCAL.[1,CEG]" at SU-AI
It would be nice if everyone would not arbitrarily adjust the varian.
Since the controls are very sensitive and it sometimes takes hours to
get the printer to track correctly again, there will have to be a
standard policy of ALL hands off.
The problems we have been experiencing for the past few days and the reason
it has taken so long to adjust, is that someone took the rubber ring
off the nylon end of the roll paper holder thus, the paper was allowed to
shift back and forth on the unaligned paper guide.
Please do not take anything off the varian. Each piece has a place and a
purpose, so if it don't fit you're doing something wrong.
If you have any questions, the operator's guide will be posted near the
Varian for easy referance and I am available anytime during the day.
Roland